In a DRAM (dynamic random access memory), capacitors are used to store data in the cell, and therefore, the capacitors have to be refreshed to preserve the cell data. There are several methods for refreshing such DRAM cells.
For example, the RAS(row address strobe) Only Refreshing method (more popularly known as "ROR") refreshes the cells by changing only RAS signals while keeping CAS (column address strobe) signals constant at a high level. This ROR method has disadvantages in that addresses have to be externally provided during refresh operations, and address buses cannot be used for other purposes during refresh operations.
There is another refresh method known as "CBR" (CAS Before RAS). When memory cells are accessed during normal operations, generally RAS signals are changed before CAS signals are. In this CBR refresh method, to recognize a refresh mode, CAS signals are changed before RAS signals are, thus allowing refresh operations to be carried out under the refresh mode. This CBR refresh method also has disadvantages in that to generate addresses within the DRAM, an internal refresh counter can not be externally controlled.
FIG. 1 shows such a CBR refresh detecting circuit, and FIG. 2 shows such a refresh counter. This CBR refresh detecting circuit includes an invertor I1 for receiving RAS signals externally provided thereto; an invertor I2 for receiving the output of the invertor I1; and an invertor I3 for receiving CAS signals externally provided thereto. The detecting circuit further includes a transmission gate TS1, i.e., basically a switch composed of a PMOS transistor and an NMOS transistor connected in parallel. The gate of the PMOS transistor receives the output of the invertor I1, while the gate of the NMOS transistor receives the output of the invertor I2. The input of TS1 is connected to the side of the invertor I3, and the output of TS1 is connected to the input of a latch I4.
Under the refresh mode, refreshing is carried out by generating addresses from a counter provided within the DRAM. The latch I4 and a latch I5 jointly constitutes a latch, and a 2-input NOR gate NR1 receives the output of the invertor I2 on one input and the output of the latch I4 on the other, and outputs CBR signals.
Referring to FIG. 2, the refresh counter is composed of a plurality of T type flip-flops (T-F/Fs) connected in cascade. The first stage T-F/F of the refresh counter receives the CBR signal as a clock signal, and each subsequent stage T-F/F uses an inverted output QB of the preceding stage as a clock signal. A non-inverted output Q of each stage of the refresh counter, i.e., A0, A1, . . . An-2, and An-1, is provided to an address buffer to serve as a refresh address when the refresh control circuit is under the CBR refresh mode.
FIG. 3 is a timing chart associated with the operation of the CBR refresh detecting circuit of FIG. 1. Suppose that the RAS signal, which is externally provided to the invertor I1, is high, then the output of the invertor I1 becomes low. Likewise, suppose that the CAS signal is high, then the output of the invertor I3 becomes low. Then the NMOS gate (the output of the invertor I2) of TS1 becomes high, and the PMOS gate (the input of the invertor I1) becomes low, thereby activating (or turning on) TS1. Therefore, the output of TS1 becomes low (same as the output of the invertor I3), and the output of the latch I4 becomes high, and consequently the CBR signal becomes low.
When the refresh control circuit is not under the CBR refresh mode, the RAS signal becomes low before the CAS signal does. Then, the output of the invertor I1 becomes high, and the output of the invertor I2 becomes low. Consequently, TS1 is turned off, and the latches I4 and I5 form a latch, and the output of the latch I4 consequently stays high, thereby making the CBR signal stay low.
When it is under the CBR refresh mode, the CAS signal becomes low before the RAS signal does. Accordingly, TS1 is turned on, the output of the invertor I3 is shifted to high, while the output of the latch I4 is shifted to low to latch. When the RAS signal subsequently becomes low, TS1 is turned off, and the output of the invertor I2 becomes low. Therefore, the CBR signal becomes high. The RAS signal becomes high and stays high until the output of the invertor I2 becomes high.
FIG. 4 is a timing chart associated with the operation of the refresh counter of FIG. 2. T-F/Fs reverse the signal state of the non-inverted output Q when the clock is shifted from low to high. Suppose that the initial state of the output of each T-F/F is set to low. Then, if the CBR signals are shifted from low to high, the output Q of the first stage T-F/F of the counter is shifted from low to high. If the CBR signal is shifted in the sequence of high.fwdarw.low.fwdarw.high, then the output Q of the first stage T-F/F is shifted from high to low, and the output QB is shifted from low to high.
When the CBR signal is shifted in the above sequence repeatedly, the first stage T-F/F repeats the shifting sequence of low.fwdarw.high.fwdarw.low.fwdarw.high, and since the second stage T-F/F uses the output QB of the first stage (i.e., QB of the first stage repeats the sequence of high.fwdarw.low.fwdarw.high.fwdarw.low), when the output QB of the first stage is shifted from low to high, the output Q of the second stage is shifted from low to high. In this manner, the refresh counter operates as a ripple counter.
Of the above described conventional refresh methods, in the CBR refresh method, the internal address counter can not be externally controlled, i.e., can not be reset to an arbitrarily selected value, and therefore, the CBR refresh method can not be used in conjunction with the ROR refresh method. Further, in the ROR refresh method, address buses can not used for other purposes during the refresh operation.